The present invention relates to a mask pattern checking system in which the presence or absence of pattern defects on a mask used for the exposure of patterns on wafers in fabricating semiconductor devices such as ICs and LSIs is checked through comparison with design data. The invention particularly relates to bit pattern generator in such a system for automatically generating bit patterns based on the design data.
FIG. 1 shows in block diagram a mask pattern checking system to which the present invention is applicable. The system comprises a memory 1 having stored design data, a computing circuit 2, a bit pattern generator 3, a defect determination circuit 4, a pattern detecting sensor 5, a binary encoder 6, a clock generator 7, and a mask 8 under test. The binary encoder 6 receives the output of the pattern detecting sensor 5 to provide binary data in the sequence of i=0; j=0, 1, 2, . . . , n: i=1; j=0, 1, 2, . . . , n: corresponding to the mask pattern image scanned by the pattern detecting sensor 5 as exemplified in FIG. 3. The bit pattern generator 3 generates reference patterns in synchronism with the output from the pattern detecting sensor 5 on the basis of the start point and end point addresses X.sub.s1, X.sub.e1 ; X.sub.s2, X.sub.e2 ; . . . ; X.sub.sm, X.sub.em on the pattern existing coordinate j for each scanning line which addresses are produced by the calculation from apex coordinate date each pattern stored in the memory 1, as shown in FIG. 2.
As shown in FIG. 3, the conventional form of the bit pattern generator 4 comprises a number of pattern generator circuits 3.sub.l -3.sub.n which suffices for coordinate data X.sub.s1, X.sub.e1 ; X.sub.s2, X.sub.e2 ; . . . ; X.sub.sm, X.sub.em. Each pattern generator circuit includes latch circuits 10 and 11 for X.sub.s and X.sub.e, comparators 12 and 13 for comparing latched data with the count X.sub.ck of a scanning address counter 15, and an AND gate 14 for producing a logical product between the outputs of the comparators 12 and 13. The bit pattern output from each of the generator circuits 3.sub.l -3.sub.n are generated through an OR gate 16 on a real time basis in synchronism with the scanning clock signal.
However, as the integration of semiconductor devices has advanced much higher recently, the number of data X.sub.s and X.sub.e to be processed by the bit pattern generator increases, resulting in a complex circuit arrangement including a large number (200-300 sets or more) of pattern generator circuits 3.sub.l -3.sub.n. This also requires long wiring, causing problems of signal propagation time, and it is difficult to generate bit patterns at high speed in synchronism with the pattern detecting sensor.